Design verification Engineer

For Job description, Key words - Design verification - UVM - Low power - ARM , AXI, APB, AHB - UPF - Gate Level Simulation GLS - At least 7-8 years of experience with pre-silicon DV. - Knowledge and hands on experience with Verilog, System Verilog , UVM, debugging waveforms . - Must be proficient with : building a testbench for a medium complexity block using System Verilog and UVM . - Writing random tests, directed tests, error tests & performance tests for a block of medium complexity using System Verilog and UVM. - Developing, maintaining and supporting of the UVM verification environment. - Debugging tests with design engineers to deliver functionally correct design blocks . - OOPS, randomization, constraints, interfaces writing & analyzing functional coverage, assertions . - Generating and analyzing code coverage