Design Verification Simulation Principal Engineer -

Job Details

  • ID#44895520
  • Address 73301 , Austin,

    Texas

    Austin USA
  • Job type

    Contract

  • Salary USD Depends on Experience Depends on Experience
  • Hiring Company

    Indotronix International Corp

  • Showed15th August 2022
  • Date26th July 20222022-07-26T00:00:00-0700
  • Deadline24th September 2022
  • Category

    Et cetera

Design Verification Simulation Principal Engineer -

  • Category: Et cetera
  • Deadline: 24th September 20222022-09-24T00:00:00-0700
  • Texas

Vacancy expired!

Primary Skill: Python

Onsite Positions

Locations: Austin, San Jose, PhoenixResponsibilities:The ideal candidate should have 3-5+ years of Gate-Level Simulation experience.Expertise with debugging in Best/Worst SDF with min/max corner simulations.Understanding of various timing violations and identifying them as waiver or real netlist issues by working closely with design and architecture teams.Experience with timing constraints and multi clock domain designRun tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes.Engage with the team to drive continuous improvement to the verification env to find more bugs and improve coverageWork as a team to grow together. Mentor and coach junior team membersPower-Aware simulation experience is desirable.

Vacancy expired!