Design Verification & Gate Level Simulation Principal Engineer

Job Details

  • ID#44906736
  • Address 73301 , Austin,

    Texas

    Austin USA
  • Job type

    Contract

  • Salary USD Depends on Experience Depends on Experience
  • Hiring Company

    Y & L Consulting Inc.

  • Showed16th August 2022
  • Date09th August 20222022-08-09T00:00:00-0700
  • Deadline08th October 2022
  • Category

    Et cetera

Design Verification & Gate Level Simulation Principal Engineer

  • Category: Et cetera
  • Deadline: 08th October 20222022-10-08T00:00:00-0700
  • Texas

Vacancy expired!

Position: Design Verification & Gate Level Simulation Principal Engineer

Contract Duration: 9 Months + Several Possible Extensions

Work Site: Onsite work is REQUIRED in Austin, TX

Primary Skill: Python

Responsibilities:
  • The ideal candidate should have 3-5+ years of Gate-Level Simulation experience.
  • Expertise with debugging in Best/Worst SDF with min/max corner simulations.
  • Understanding of various timing violations and identifying them as waiver or real netlist issues by working closely with design and architecture teams.
  • Experience with timing constraints and multi clock domain design
  • Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes.
  • Engage with the team to drive continuous improvement to the verification env to find more bugs and improve coverage
  • Work as a team to grow together. Mentor and coach junior team members
  • Power-Aware simulation experience is desirable.1 - C (Programming Language) (P3 - Advanced) |2 - C Programming Language (P3 - Advanced) |3 - Industry X IOT Applications (P3 - Advanced) |4 - PERL Scripts (P3 - Advanced)

Vacancy expired!