Job Details

  • ID#45405246
  • Address 73301 , Austin,

    Texas

    Austin USA
  • Job type

    Contract

  • Salary USD $90 - $100 90 - 100
  • Hiring Company

    Technical Link

  • Showed03rd September 2022
  • Date02nd September 20222022-09-02T03:00:00-0400
  • Deadline01st November 2022
  • Category

    Et cetera

ASIC STA Engineer

  • Category: Et cetera
  • Deadline: 01st November 20222022-11-01T03:00:00-0400
  • Texas

Vacancy expired!

Responsible for high performance CPU STA sign-off, power recovery, and timing closure. Perform block level STA environment setup including constraints development, STA regression execution, and timing, power eco generation. Work closely with RTL/DFT teams to define timing constraints for functional and DFT modes. Participate in world-wide STA forum and contribute to defining leading edge STA margin methodologies. Responsible for delivering timing models (ETM, Hyperscale) and timing deliverables (SDC, timing budgets), and support successful integration at SOC level.

Job requirements:
  • 5+ years of hands on experience in STA of high performance CPU design with frequencies > 2 Ghz.
  • Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains.
  • Solid understanding of multi-scenario STA and timing constraints.
  • Excellent understanding of margining methodologies (OCV/AOCV/POCV) to address process variation, correlation to spice, silicon.
  • Experience with design closure across a wide range of operating points (multi-OPP), addressing setup-hold conflicts due to transistor/wire scaling.
  • Experience with clock tree analysis and drive physical implementation to achieve a scalable clock tree implementation for smooth timing convergence.
  • Experience with custom recipe development for timing closure and power recovery in sign-off tool environment to achieve best in class power efficient high performance CPU.
  • Knowledge of low-power techniques, familiarity with multi-voltage island design specification (CPF/UPF).
  • Strong skills with Cadence and Synopsys timing sign-off flows.
  • Strong scripting skills in tcl, perl, or python.
  • Experienced in working on advanced process nodes (16nm).

Plus:
  • ARM CPU STA experience
  • Familiarity with implementation flows (synthesis, place and route, physical verification)
  • IR Drop analysis (Static & Dynamic)

Vacancy expired!

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