ASIC RTL Designer
Vacancy expired!
Job DescriptionThe Senior RTL Design Engineer will be responsible for Micro-architecture, RTL coding/integration, Synthesis of complex IP and ARM CPU subsystems. Run RTL quality checks (Lint, Equivalence checks, CDC…) to ensure quality of RTL. Synthesize the design and provide timing constraints to the Physical Design team to ensure RTL meets timing. Work with DV team to define the test plan and verify the RTL thoroughly. Work with WW teams to align on the specification and deliverables.RequirementMinimum Requirements
- BS or MS degree in Computer Engineering or Electrical/Electronic Engineering
- 8+ Years of experience in RTL design of Complex IP and/or CPU Sub-systems
- Good understanding of the High Performance ARM CPU architecture and familiarity with latest High Performance ARM cores
- Expert in RTL Coding/Integration and Synthesis
- Prior experience in all Front End activities and quality checks (eg: Lint, CDC)
- Good understanding and working knowledge in other domains like DV and DFT, timing closure
- Able to provide timing constraints and work with PD teams to ensure RTL meets timing
- Strong debugging and scripting skills (Perl, Python, Tcl)
- Ability to work with DFT teams to improve test coverage
- Ability to work with WW teams to align on specifications and deliverables
- Good communication
- Prior experience in RTL integration of ARM CPU subsystems
- Experience with multi-power domain design
- Prior Silicon debug experience