Sr. ASIC Verification Engineer
- Category: Et cetera
- Deadline: 15th July 20232023-07-15T00:00:00-0700
- California
Vacancy expired!
ASIC Verification Engineer for Leading Communications CompanyThis Jobot Job is hosted by: Stephen MarodaAre you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume.Salary: $120,000 - $180,000 per yearA bit about us:We are an industry leader and Fortune 100 company defining the US communications equipment market.Why join us?Excellent CompensationBright team members with great technical depth. RSU's program. Exceptional Corporate benefits.Job DetailsQualifications
- Typically requires MSEE/CS combined with 3-5 years of related experience, or BSEE/CS combined with 4-6 years of related experience
- Must be proficient in SystemVerilog/UVM. Knowledge of Linux is essential. C/C and Python/Perl are preferred.
- Must be familiar with ASIC design and verification processes, methodology and tools. Must have strong debugging skills (post-silicon lab bring-up experience is a plus). Knowledge of Networking is preferred. Experience with Formal verification is a plus.
- Requires good communication skills to interface with the hardware, software designers and vendors
- Understands product level architecture
- Will participate in the ASIC design verification or high-end switching products
- Responsibilities include the development of simulation models, test plan, direct and random tests, code or functional coverage,
- Ability to solve problems of moderate scope involving multiple modules
- Shares information and communicates clearly to team members