Design Verification Engineer with UVM

This Jobot Job is hosted by: Pat CareyAre you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume.Salary: $50 - $115 per hour

A bit about us:We are a software consulting and development company based in the Bay area.

Why join us?Great Pay!Great Culture!Long term work!

Job DetailsDesign Verification Engineer-Remote RoleEducation Requirements

• BS/MS in EE/CE, plus 5+ years of Design Verification experience
• Familiarity with ASIC, Computer and Embedded Systems Architectures
• Excellent oral and written communication skills with people at all levels, a must.
• Team player, with excellent debugging skills

Mandatory Experienceo Writing and maintaining test planso Creating and maintaining UVM testbencheso Created a module testbench from scratcho Written Cover points, Assertions (SVA) and closed coverageo Knowledge of standard bus protocols such as AHB, AXI, etc.Desirable Experienceo Scripting and test automation for regressiono Experience with PCIe/NVMe and/or ONFIo Experience with SSD architectureInterested in hearing more? Easy Apply now by clicking the "Apply Now" button.