Job Details

  • ID#37677837
  • Address 95101 , Sanjose,

    California

    Sanjose USA
  • Job type

    Permanent

  • Salary USD Based on Experience Based on Experience
  • Hiring Company

    Jobot

  • Showed04th April 2022
  • Date03rd April 20222022-04-03T03:00:00-0400
  • Deadline02nd June 2022
  • Category

    Security

ASIC/SOC designer

Vacancy expired!

Series be funded startup 20+ million, working on security management chips and cores to prevent hackers. Great equity options, blue cross blue shield- health insurance.This Jobot Job is hosted by: Barrett DavisAre you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume.

A bit about us:A security processor company redefining hardware root of trust with hardware-based security technologies, including per-system AI.

Why join us?Great product working on Security system processors and is an AI-powered engineer to prevent hackers. Great equity options based on experience, and working with a strong team in the bay area.

Job DetailsASIC/ SOC designer- RTL logic design and implementation, microarchitecture, timing closure, coding in verilogBig plus for embedded CPU design. Onsite in San Jose, California. Full Job description below.Help develop the design and implementation of SoCs;Micro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks;Top-level and block-level performance, bandwidth, power, and cost analysis and optimization;Work with FPGA engineers to perform early prototyping; andSupport test program development, chip validation, and chip life until production maturity.Team Management and BuildingCollaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.Qualifications5+ years of experience in RTL logic design, verification, synthesis, and timing optimization;Proficient in writing clear, implementable micro-architecture specifications;Expertise in writing efficient RTL code in Verilog;Good understanding of assertions, coverage analysis, synthesis, and timing closure;Experience in revision control, regression, and bug-tracking tools;Fluency with scripting languages (e.g., Perl, Python);Must have gone through at least one tape out;Preferred: Lab debug/bring-up experienceACADEMIC CREDENTIALSBA or MS (preferred) degree in EE/EECS/CS or equivalent.Interested in hearing more? Easy Apply now by clicking the "Apply Now" button.

Vacancy expired!

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